Abstract:
High Efficiency Video Coding (HEVC) involves variable size higher order Discrete Cosine Transform (DCT) to increase coding efficiency. However, higher order DCT increases the hardware complexity, thereby increasing the area and power consumption of the physical design. In this paper, a new method to derive higher order DCT is presented. The proposed method uses rotation based structures and uses trigonometric relations to decompose those structures. Finally, all the floating point coefficients of the rotation unit are approximated by dyadic values such that they can be realized by add and shift operation. Hence, the proposed method eliminates the need for multipliers and significantly reduces the complexity of the core transform for HEVC. The proposed approach is used to design all size of DCT supported by HEVC and can be further extended to design larger size DCT and IDCT to be used in the near future for image and video compressions. The proposed architecture has a maximum throughput of 3.2 Gsps and is capable of processing at least 30 frames/s of ultra high definition 3840 × 2160 video. Experimental results demonstrate that the proposed design method maintains similar coding efficiency, but requires 24% less area-delay product and 25% less power compared to the HEVC reference algorithm. © 1991-2012 IEEE.
