Browsing Department of Electronic Engineering by Subject "Selective buried oxide (SELBOX)"

Now showing items 1-2 of 2

Investigation of DC, RF and linearity performances of a back-gated (BG) heterojunction (HJ) TFET-on-selbox-substrate (STFET): Introduction to a BG-HJ-STEFT based CMOS inverter

Singh, A.K.; Tripathi, M.R.; Baral, K.; Singh, P.K.; Jit, S. (Elsevier Ltd, 2020-08)

This manuscript reports the back-gate effects on device-level performance of a heterojunction TFET on SELBOX substrate (HJ-STFET). The proposed structure implements a stacked gate oxide where the conventional SiO2 is ...
Simulation Study and Comparative Analysis of Some TFET Structures with a Novel Partial-Ground-Plane (PGP) Based TFET on SELBOX Structure

Singh, A.K.; Tripathi, M.R.; Chander, S.; Baral, K.; Singh, P.K.; Jit, S. (Springer, 2020-10-01)

This paper proposes a novel TFET structure namely gate stacked (GS) heterojunction (HJ) partial-ground-plane (PGP) TFET with SELBOX (GSHJ-PGP-STFET) for improving the ON/OFF-state current ratio of the TFET by reducing the ...

Now showing items 1-2 of 2

Search in IDR