SHJ Solar Cells on an Adequately Thin c-Si Wafer with Dome-Like Front and Double-Layer ITO Nanoparticles as Rear Light Trapping Arrangements

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dc.contributor.author Dikshit, Ashutosh Kumar
dc.contributor.author Das, Gourab
dc.contributor.author Mukherjee, Nillohit
dc.contributor.author Chakrabarti P.
dc.date.accessioned 2023-04-26T08:04:56Z
dc.date.available 2023-04-26T08:04:56Z
dc.date.issued 2022-01
dc.identifier.issn 00189383
dc.identifier.uri http://localhost:8080/xmlui/handle/123456789/2306
dc.description This paper is submitted by the author of IIT (BHU), Varanasi, India en_US
dc.description.abstract This present work describes the fabrication of silicon heterojunction (SHJ) solar cells as a proof-of-concept scheme on an adequately thin ( $30 ~\mu \text{m}$ ) n-type crystalline silicon (c-Si) wafer as the active layer. The thickness of the cell, in this case, is five to six times lower than any c-Si-based conventional solar cell technology. The work has been initiated to go in line with the recommendations of the International Technology Roadmap for Photovoltaics (ITRPV) in 2019 on the 'thinning' of silicon-based solar cells to achieve cost-effectiveness of the modules. To address light-trapping-related issues in thin silicon substrate, dome-like front texturization and indium tin oxide (ITO) compact layer/nanoparticle (NP) array as the back reflecting configurations have been adopted. Dome-like front textured surface helped in conformal deposition of the front amorphous layers, improving the shunt resistance, open-circuit voltage, and fill factor of the cell. On the other hand, a properly placed array of single and double layers of ITO NPs notably increased the back reflection of light with wavelengths >700 nm, resulting in improved short-circuit current density and conversion efficiency. Comparative investigations have been carried out to explore the influence of different ITO-based back reflecting structures on the cell parameters with detailed optical and electrical characterization. We have reported 15% conversion efficiency with an n-type as-cut c-Si wafer having a carrier lifetime of $100 ~\mu \text{s}$. en_US
dc.language.iso en_US en_US
dc.publisher Institute of Electrical and Electronics Engineers Inc. en_US
dc.relation.ispartofseries IEEE Transactions on Electron Devices;IEEE Transactions on Electron Devices
dc.subject Double back reflection layer en_US
dc.subject Indium tin oxide (ITO) nanoparticle (NP) en_US
dc.subject light trapping en_US
dc.subject Proper positioning en_US
dc.subject Silicon heterojunction (SHJ) solar cell en_US
dc.subject Thin crystalline silicon (c-Si) wafer en_US
dc.title SHJ Solar Cells on an Adequately Thin c-Si Wafer with Dome-Like Front and Double-Layer ITO Nanoparticles as Rear Light Trapping Arrangements en_US
dc.type Article en_US


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